1) Field of the Invention
This invention relates generally to fabrication of capacitors in a DRAM cell and more particularly to a method and process for fabricating T-Shaped capacitors with a large capacitance.
2) Description of the Prior Art
A dynamic random access memory (DRAM) cell is in general a semiconductor memory device with one transistor and one capacitor, in which a data of one-bit can be stored in the capacitor by the charge stored therein. As a tendency to raise the density of an integrated semiconductor device causes the density to the DRAM cells to be increased, the area occupied by the one memory cell becomes gradually decreased. Therefore, the present invention is devoted to the manufacture of a capacitor with a maximum capacity in a limited area with a minimum number of photolithographic steps
Semiconductor technologies have dramatically increased the circuit density on a chip. The miniaturized devices built in and on semiconductor substrate are very closely spaced and their packing density has increased significantly. More recent advances in photolithographic techniques, such as phase-shifting masks, and self-aligning process steps have further reduced the device sized and increased circuit density. This has lead to ultra large scale integration (ULSI) with minimum device dimensions less than a micrometer and more than a million transistors on a chip. With this improved integration, some circuit elements experience electrical limitation due to their down sizing.
One such circuit element experiencing electrical limitations is the array of storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field effect transistor (MOS-FET) and a single capacitor are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of the memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
FIGS. 1A-1C represent prior art fabrication processes for forming a capacitor. In FIG. 1 A, a field oxide layer 112 for the separation of respective cells is formed in a portion of a substrate 110 of a first conductivity. Then, in order to prepare a source region 118, a layer of second conductivity is formed by an ion injection near the field oxide layer 112. A drain region 120 separately distanced from the field oxide layer 112 is formed. A first oxide layer 122 covers the entire surface of the substrate 110 except some parts of the source region 118. Between the source and drain regions 18, 20, a gate electrode 116 is formed thereon, while a gate oxide layer 114 is provided as an intermediate layer. Thereafter, a source contact region 123 is formed by etching the first oxide layer 122 on the source regions 118, in a manor of a conventional etching process.
In FIG. 1B, after formation of the first polycrystalline silicon layer over the source region 118, a storage electrode 124 is formed by etching the predetermined region of the first polycrystalline layer.
In FIG. 1C, the capacitor having a typical stacked structure is completely fabricated by forming a plate electrode 128 along the top surface of a dielectric layer 126 by etching a predetermined region after spreading the dielectric layer 126 on the surface of the storage electrode 124 and by forming a second polycrystalline silicon over the entire surface of the substrate 110. In a conventional stacked-capacitor, as shown in FIG. 1C, when the area occupied by a cell is reduced, the areas occupied by the storage electrode 124 and the plate electrode 128 are also reduced. Therefore there is a problem in that sufficient capacity required in a high density memory device of more than 64 mega bits can not be made using conventional lithography techniques unless a method is developed that further miniaturizes the size of the storage electrode below photo dimensional limitations.
Generally, in a 54 MB DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and structured capacitors. However, the processes used to make these three dimensional capacitors are complicated and expensive. Therefore a method is need to fabricate a stacked capacitor having a size smaller that that capable by lithographic processes and which is uncomplicated.
The following U.S. patents show related processes and capacitor structures: Miyake, U.S. Pat. No. 5,403,766; and Keum et al. U.S. Pat. No. 5,432,116. However, many of the prior art methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. Also, other process methods rely on etching to a predetermined etch depth which can be quite difficult to control in a manufacturing environment. For example, during plasma etching outgassing, virtual or real leaks, back streaming from pumps and loading effects, to name a few, can change the chemistry of the etching environment in the process chamber, making a calibrated etch time approach difficult to control. Therefore, it is very desirable to develop processes that are as simple as possible and also provide methods for monitoring, in situ, the etch depth during processing.
There is a challenge to develop methods of manufacturing these capacitors that minimize the manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method which minimizes the number of photoresist masking operations and to provide maximum process tolerance to maximize product yields. There is also a challenge to develop a capacitor that is not limited in size by the photolithographic techniques.